Chip-Off NAND Data Recovery

BGA rework uses controlled heat profiles to desolder NAND packages from the PCB without thermal damage to the silicon die. Each chip is then read individually, and the raw data is reconstructed by decoding the controller's interleaving and error correction algorithms.

1. 01

   NAND Identification

   NAND flash chips are identified and cataloged on the PCB. Manufacturer, part number, die configuration, and number of chips are recorded. This determines the correct reader adapter and decoding parameters.

2. 02

   Underfill Removal & Controlled Desoldering

   Some SSD manufacturers apply epoxy underfill adhesive beneath NAND BGA packages to improve shock resistance. This adhesive bonds the chip to the PCB & must be softened or chemically dissolved before desoldering can begin. Attempting to desolder a chip through cured underfill rips the copper pads off the PCB & fractures the silicon die.

   After underfill is cleared, the Zhuo Mao BGA rework station heats each NAND package at precise temperature profiles to melt the solder balls without exceeding the thermal limits of the silicon die. Overheating destroys the NAND. Underheating tears pads from the PCB. Both are irreversible.

3. 03

   Raw NAND Reading

   Cleaned chips are placed in a chip reader (PC-3000 Flash reader or equivalent). Raw hex data is dumped from each chip. This data is scrambled; it is not a readable file system.

4. 04

   Interleaving and ECC Reconstruction

   The controller's specific data interleaving pattern (how it striped data across multiple chips) must be reverse-engineered. ECC (Error Correction Code) algorithms are applied to correct corrupted pages. The Flash Translation Layer and block mapping are reconstructed manually.

5. 05

   File System Extraction

   Once the logical data layout is rebuilt, the file system is extracted and verified against expected directory structures. Files are delivered on your choice of return media.

Controller repair is always attempted first. PC-3000 firmware recovery and board-level microsoldering preserve the original controller and its encryption keys. Chip-off is destructive, requires more labor, and cannot recover data from encrypted drives at all. We escalate to chip-off only after confirming the controller cannot be revived.

The escalation path for every SSD that arrives at our lab follows a strict order. First, we attempt firmware corruption recovery using the PC-3000 to communicate with the controller in technological mode. If the controller responds, we recover data without touching the hardware.

If the controller does not respond, we move to board-level repair: Hakko microsoldering to replace burned voltage regulators, rework cold solder joints on the controller BGA, or replace passive components. The goal is to restore enough controller functionality for PC-3000 access. If the controller silicon itself is cracked or burned through, and the drive does not use hardware encryption, chip-off is the final option.

We will tell you before starting chip-off if the drive uses hardware encryption. If it does, and the controller is beyond repair, we will tell you the data is unrecoverable rather than charge you for work that cannot succeed.

Home chip-off attempts destroy the NAND silicon before any data can be read. The procedure requires a PC-3000 Flash reader, a Zhuo Mao BGA rework station with thermocouple-controlled profiles, BGA stencils matched to the chip's ball pitch, & controller-specific reconstruction software. The equipment alone costs over $10,000.

A consumer heat gun can't hold the 1.5 to 2.0°C/s ramp rate that SAC305 solder requires. It overshoots the 245°C peak within seconds, cracking the NAND die through thermal shock. One wrong temperature profile, & the only copy of your data is gone permanently.

Even if the chip survives extraction, the raw hex dump isn't readable. The controller's XOR scrambling keys, interleaving pattern, & FTL mapping must be reverse-engineered before a single file appears. PC-3000 Flash includes controller-specific modules for Phison and Silicon Motion reconstruction. Without that software, a raw NAND dump is noise.

Budget NAND Programmers Can't Reconstruct SSD Data

Forum posts recommend budget IC programmers (XGecu T48, TL866II+) for chip-off attempts. These devices cost under $200 & can read raw binary data from an unencrypted NAND or eMMC chip. The read step works. The reconstruction step doesn't.

A budget programmer dumps a binary blob with no understanding of the controller's XOR scrambling, interleaving order, or ECC algorithm. PC-3000 Flash includes controller-family-specific reconstruction modules that decode these parameters automatically for supported legacy flash families (older Phison and Silicon Motion controllers). A generic programmer produces a raw hex file that looks like random noise. The read hardware isn't the bottleneck; the reconstruction software is.

Lead-free BGA NAND packages use SAC305 solder (96.5% tin, 3% silver, 0.5% copper) with a solidus temperature of 217°C and a liquidus of 220°C. Extracting the chip requires a multi-stage thermal profile that raises the PCB temperature gradually to prevent thermal shock, die delamination, and the “popcorn effect” where trapped moisture causes catastrophic package cracking.

Heating a NAND package directly with a hot air gun without preheating the substrate creates a steep thermal gradient between the chip and the surrounding PCB. This differential warps the board, tears solder pads, and can fracture the silicon die internally. The Zhuo Mao BGA rework station used in our lab applies controlled bottom-side IR preheat to the entire PCB while the top-side nozzle targets only the NAND package. The Atten 862 hot air station handles smaller packages and precision touchup work.

Lead-Free NAND Extraction Thermal Profile

Temperature is measured via thermocouple at the solder joint under the BGA package, not at the nozzle exhaust. Nozzle readings do not reflect actual joint temperature and are unreliable for process control.

Atten 862 for Smaller Packages & Precision Touchup

The Zhuo Mao handles full-size BGA-152 & BGA-132 NAND packages on standard 2.5" SATA SSD boards. Smaller packages need different tooling. TSOP-48 chips on older USB flash drives, single-chip NAND packages on compact M.2 drives, & monolithic devices with exposed test pads all sit close to neighboring components that can't tolerate the Zhuo Mao's broader heat zone.

The Atten 862 hot air station addresses this gap. Its smaller nozzle diameter concentrates airflow on the target package without heating adjacent ICs or capacitors. Adjustable airflow rate (measured in liters per minute) prevents the thin M.2 PCB substrate from flexing during localized heating. After initial extraction on the Zhuo Mao, the Atten 862 handles precision touchup: cleaning residual solder from exposed PCB pads, reflowing stray solder bridges, & prepping the pad field for inspection under the stereomicroscope before the chip moves to the reader.

NAND Chip Reballing After Extraction

Extracted BGA NAND chips can't go straight into a reader socket. The desoldering process leaves irregular solder residue on the chip's ball pads: flattened remnants, bridged contacts, & oxidized surfaces that prevent reliable electrical connection with the PC-3000 Flash reader's ZIF socket pins.

Pad cleaning comes first. A Hakko FM-2032 iron with a fine chisel tip & copper solder wick removes residual solder from each pad. Chemical flux residue is washed off with isopropyl alcohol under the stereomicroscope. Clean, flat copper pads are the starting point for fresh solder ball placement.

Reballing uses a laser-cut stainless steel BGA stencil matched to the chip's ball pitch (typically 1.0mm for BGA-152 and BGA-132 NAND packages). The stencil aligns over the cleaned pads, solder paste is applied through the apertures, & a controlled reflow at 235 to 245°C forms uniform spherical contacts. The result: a chip with consistent solder ball geometry that seats cleanly in the reader's ZIF adapter.

The Multiboard carrier approach skips reballing entirely. Instead of restoring the BGA ball grid, the chip is soldered directly to a disposable carrier board that plugs into the PC-3000 Flash reader. Soldered connections provide higher signal integrity than ZIF socket contact, which matters on TLC & QLC NAND with tight read voltage margins. The tradeoff: each carrier is single-use.

Raw NAND data is not a readable file system. The controller applied error correction codes (ECC), data scrambling via XOR transforms, and proprietary interleaving before writing to the NAND. Chip-off recovery must reverse all three transformations to reconstruct usable data from the raw hex dump.

BCH vs. LDPC Error Correction

NAND flash cells degrade with each program/erase cycle. Electrons leak from floating gates, and read operations disturb adjacent cells. Controllers append ECC data to the spare area (Out-Of-Band region) of every NAND page to detect and correct bit errors before the host sees the data.

BCH (Bose-Chaudhuri-Hocquenghem)

The standard ECC algorithm for SLC and MLC NAND. BCH uses algebraic hard-decision decoding: each cell is read as binary 1 or 0. During chip-off recovery, the BCH polynomial can be detected from the raw dump and applied to correct bit errors. PC-3000 Flash supports automated BCH correction.

LDPC (Low-Density Parity-Check)

Required for TLC and QLC NAND where the raw bit error rate exceeds BCH's correction capacity. LDPC uses soft-decision decoding: instead of reading a simple 1 or 0, the controller takes multiple voltage measurements per cell to estimate the probability of the bit state. Chip-off recovery loses the controller's hardware LDPC engine. Reconstructing LDPC corrections from a raw hard-decision dump is computationally intensive and may require the original controller's read-retry voltage offset tables to decode heavily degraded pages.

Page Scrambling and XOR Key Extraction

Flash controllers scramble all data before writing it to NAND. This is not encryption; it is a data-integrity measure that prevents adjacent cells from holding identical charge states (which accelerates charge leakage). The controller generates a pseudo-random key and XORs it with the user data. Recovery requires XORing the raw dump with the same key to reverse the transformation.

XOR keys can be extracted by finding NAND regions the operating system filled with logical zeros (0x00). Since 0x00 XOR Key = Key, zero-filled regions store the pure scrambling key. NAND reconstruction tools scan physical dumps for repeating vertical bit patterns with distinctive geometric shapes (triangles, diagonals), which indicate an extractable XOR key.

Recovering Corrupted XOR Keys from Degraded NAND

On degraded NAND, the zero-filled regions used for XOR key extraction contain bit errors. A corrupted XOR key applied to the raw dump produces partially descrambled data: some pages decode cleanly while others remain noise. The fix is a bitwise majority vote across multiple key samples.

The engineer locates three or more separate NAND blocks known to contain zero-fill patterns (typically found at the end of the user partition or in unwritten spare capacity). Each block stores its own copy of the XOR key, but each copy has different random bit flips from NAND cell degradation. PC-3000 Flash compares these samples bit by bit. For each bit position, the tool takes the majority value across all samples: if two out of three copies read “1” at position N, the correct key bit is “1.” Random bit errors don't cluster at the same positions across physically separate blocks, so the majority vote cancels them out & produces a clean key.

Dynamic XOR keys (used by Phison & newer Silicon Motion controllers) add a complication: the key changes per virtual block based on a static base key combined with a page-address-dependent seed. The majority-vote process must first isolate the static base component, then identify the dynamic seed generation algorithm. On controllers where the seed is derived from the block address, the engineer can predict the per-block key once the base key is clean. On controllers with cryptographically derived seeds, the base key alone isn't enough; the seed algorithm must be reverse-engineered from known plaintext patterns in the NAND service area.

Read Retry and Voltage Calibration on Degraded NAND

When NAND cells wear out, default read voltages produce uncorrectable bit errors. The chip reader must iterate through voltage offset tables to find threshold boundaries that separate valid cell states from noise. During chip-off, this calibration happens manually because the original controller's tuning data is gone.

A healthy TLC cell stores 3 bits across 8 voltage levels separated by defined margins. After thousands of program/erase cycles, electrons leak from charge storage layers & those margins shrink. The default reference voltages that cleanly distinguished L0 from L1 now sit in the overlap zone between adjacent states. QLC is worse: 16 voltage levels per cell with tighter margins from day one.

PC-3000 Flash addresses this with configurable read-retry offset tables. The engineer shifts reference voltages in small increments (typically 50mV to 100mV steps), re-reads the page at each offset, & evaluates the ECC correction result. A working controller does this automatically using calibration data stored in its SRAM. During chip-off, that calibration data doesn't exist. The engineer tests voltage offsets empirically, page by page, until the error rate drops below the LDPC correction threshold. On a 1TB TLC drive with degraded NAND, this process can add days to the reconstruction timeline.

Controller-Specific Scrambling Patterns

Silicon Motion controllers typically use a static XOR key applied cyclically across blocks. The key length often corresponds to the block size (e.g., 128 pages), and the same key repeats for every block on the chip. Phison controllers use dynamic XOR: each virtual block gets a unique key generated from a static base key combined with a dynamic seed. The dynamic component must be identified and stripped before the static key can be applied. SandForce controllers (SF-2281) combine real-time DuraWrite data compression with hardware encryption bound to the controller silicon (marketed as AES-256, though Intel discovered a silicon-level bug in 2012 that reduced effective strength to AES-128). Regardless of key length, the encryption key is fused to the controller die, making chip-off recovery infeasible when the controller is dead.

3D NAND Extraction: Layer Variation and Vertical Crosstalk

Modern SSDs use 3D NAND that stacks memory cells vertically in 128 to 232+ layers. Chip-off on 3D NAND is harder than on older planar (2D) NAND because error rates aren't uniform across the vertical stack. Each layer can need different read-retry voltage offsets.

Planar NAND spreads cells across a flat silicon surface. Every cell sits at the same distance from the substrate, experiences the same manufacturing conditions, & degrades at roughly the same rate. 3D NAND changes that. Cells at the bottom of a 176-layer stack are formed earlier in the deposition process than cells at the top. Process variation between layers creates non-uniform threshold voltage distributions: bottom-layer cells may read cleanly at the default reference voltage while top-layer cells in the same block produce uncorrectable errors.

Vertical crosstalk compounds the problem. Adjacent cells stacked along the Z-axis interfere with each other's stored charge. Programming a cell on layer 140 shifts the threshold voltage of the cell on layer 141 through capacitive coupling. Most 3D NAND architectures use Charge Trap Flash (CTF), which stores electrons in a silicon nitride insulator layer rather than the conductive polysilicon floating gate used in planar NAND. Some manufacturers (Intel, Micron) retained floating gate designs for multiple 3D NAND generations. CTF traps charge locally, which reduces lateral cell-to-cell interference but doesn't eliminate vertical coupling between stacked layers.

During chip-off, this means the PC-3000 Flash reader can't apply a single voltage offset table across the entire chip. The engineer tests read-retry parameters per block region, adjusting for layer-dependent variation. A 1TB 3D TLC chip with 176 layers takes measurably longer to dump cleanly than a 256GB planar MLC chip of the same physical package size.

Chip-off reconstruction difficulty varies by controller family because each manufacturer implements FTL structures, XOR scrambling, & page mapping differently. The same physical extraction process yields raw NAND data, but the reconstruction software & parameter sets needed to reassemble that data into a readable file system change depending on who made the controller.

PC-3000 Flash includes controller-specific reconstruction modules. The engineer selects the correct module, loads the chip dump, & configures the block size, page size, XOR key type, & spare area format for that controller family. Getting these parameters wrong produces garbage output even when the raw dump is clean.

Phison (PS3111)

Phison stores FTL journal logs in the NAND service area rather than in dedicated DRAM. If those journal blocks are corrupted or erased, the engineer must scan every die to extract page-level metadata (LBA tags & sequence numbers) from the OOB spare areas & reconstruct the translator from scratch. The PS3111 is DRAM-less; its entire FTL lives in TLC NAND, which makes it vulnerable to corruption from P/E cycle exhaustion. Dynamic XOR scrambling on Phison generates a unique key per virtual block from a static base key combined with a dynamic seed. Both components must be identified before the data unscrambles.

Silicon Motion (SM2246EN, SM2258)

SMI uses a page mapping mode FTL with a well-defined mapping table stored in designated service blocks. The logical page number translates to a physical page number through a relatively standardized index. Static XOR keys are indexed by block size & repeat cyclically across the NAND. This cyclical pattern makes SMI reconstruction more predictable than Phison. The SM2246EN silicon supports AES encryption, but many budget drives (early Crucial & ADATA models) shipped with this feature disabled by the vendor, making those specific drives viable for chip-off extraction.

Maxio (SATA Variants)

Maxio SATA controllers (MAS0902A, MAS1102) use dynamic XOR scrambling that changes the key per page based on block address & page offset. PC-3000 Flash does not have a dedicated Maxio reconstruction module for raw NAND chip-off. Recovery from Maxio-based drives requires the original controller to be alive; PC-3000 SSD connects via SATA and uses Technological Mode to force the controller to decrypt its own data. Modern NVMe variants (MAP1602A) fuse AES-256 keys to the controller silicon, blocking chip-off entirely. If the Maxio controller is dead and board repair cannot revive it, the data is unrecoverable.

Samsung (Proprietary Controllers)

Samsung designs its own controllers (Phoenix, Elpis, Pascal) with no published FTL documentation. The block management scheme & page mapping structure differ from every other controller family. Chip-off on older unencrypted Samsung SSDs (pre-850 EVO era, before always-on encryption became standard) requires reverse-engineering Samsung-specific page markers & spare area formats that aren't shared with any other manufacturer. All Samsung NVMe drives (980 Pro, 990 Pro, 990 EVO) implement always-on AES-256 encryption, blocking chip-off entirely.

Controller identification happens during the initial evaluation. We check the markings on the controller IC, cross-reference the drive model number against our internal database, & confirm the encryption status before quoting a price. This step is free & takes minutes. It determines whether chip-off is even worth attempting on a given drive.

Always-on AES-256 encryption in modern SSD controllers has made chip-off obsolete for most drives manufactured after 2015. The controller generates a Media Encryption Key (MEK) during manufacturing, fuses it into OTP memory on the controller die, & encrypts every NAND write transparently. Desoldering the NAND yields only ciphertext.

The table below maps specific controller families to their encryption status & chip-off viability. This isn't a marketing classification; it's based on the controller's silicon architecture. A controller either has hardware encryption fuses or it doesn't.

Encrypted Controllers: Chip-Off Returns Ciphertext

Unencrypted Controllers: Chip-Off Is Viable

The MEK is generated once during manufacturing & burned into One-Time Programmable (OTP) fuses or a secure enclave on the controller die. Even without a user password set, every byte written to NAND passes through the AES engine. Moving NAND chips to a donor controller with a different MEK produces encrypted garbage; the donor's key can't decrypt data encrypted by the original.

Even on unencrypted controllers like the Phison S11, chip-off is a last resort. The S11's LDPC error correction & complex XOR scrambling make reconstruction labor-intensive. PC-3000 Technological Mode (SRAM loader injection) is always preferred because it keeps the controller's hardware ECC engine in the loop, decoding pages that a raw chip reader can't correct.

When an SSD powers on but won't mount (reports 0 bytes, enters BSY state, or identifies as “SATAFIRM S11”), the controller is alive but its firmware is corrupted. PC-3000 SSD bypasses the corrupted firmware by injecting a custom microcode loader into the controller's volatile SRAM, giving it just enough logic to read raw NAND without executing the damaged code.

Technological Mode is the reason professional labs rarely need chip-off on modern SSDs. The controller is alive; its firmware isn't. Injecting a temporary loader into SRAM sidesteps the corruption without touching the NAND physically. Firmware-level recovery using PC-3000 runs $600–$900 for SATA SSDs & $900–$1,200 for NVMe; chip-off costs $1,200–$1,500. The price difference reflects the labor difference.

SRAM Loader Injection Workflow

1. Halt the boot sequence. PC-3000 issues vendor-specific ATA or NVMe commands to stop the controller from loading its corrupted firmware modules. This prevents the controller from executing destructive operations like TRIM, garbage collection, or a factory reset that some controllers trigger on boot failure.
2. Inject the SRAM loader. A proprietary microcode payload is written into the controller's volatile SRAM. This loader gives the controller minimal read logic: enough to address NAND pages & return raw data through the SATA or NVMe interface. The loader doesn't touch the corrupted firmware stored in NAND; it runs entirely from volatile memory & disappears on power cycle.
3. Scan NAND for surviving metadata. PC-3000 reads raw NAND pages through the loader, scanning for page headers, spare area metadata, wear-level counters, & sequence numbers. It builds a virtual LBA-to-PBA mapping in host RAM, reconstructing the Flash Translation Layer without relying on the drive's corrupted FTL tables.
4. Image with real-time AES decryption. Because the original controller handles every read operation, data passes through the controller's hardware AES engine & is decrypted in real-time during imaging. The encryption key never leaves the controller. The host receives plaintext data directly.

Professional labs prefer Technological Mode over chip-off even on unencrypted drives. The controller's hardware LDPC engine stays in the loop, performing soft-decision decoding that chip-off can't replicate. A raw chip reader does hard-decision reads (binary 1 or 0); the controller does multi-pass voltage sweeps across TLC & QLC cells to calculate bit probabilities. On a worn drive with high bit error rates, that difference determines whether pages decode cleanly or return corrupted data.

SATAFIRM S11 Firmware Corruption on Phison PS3111

The Phison PS3111-S11 controller powers a large share of budget SATA SSDs: Kingston A400, PNY CS900, Patriot Burst, & dozens of OEM variants. When the S11's FTL corrupts from sudden power loss, the controller enters ROM mode & reports its identity as “SATAFIRM S11” with 0-byte capacity. The drive appears in BIOS but is inaccessible.

DIY forums recommend flashing the controller with Phison's MPTool utility. Don't. MPTool reinitializes the controller's firmware from scratch, which overwrites the FTL mapping tables. Once the FTL is gone, the link between logical addresses & physical NAND locations is destroyed. The data is still on the NAND cells, but no tool can reassemble it without the mapping.

PC-3000's Phison utility injects an SRAM loader that reads the S11's NAND without touching the corrupted FTL. The loader accesses raw pages, extracts surviving metadata from spare areas, & rebuilds the address mapping in host memory. Because the S11 doesn't implement hardware encryption, the data on the NAND is plaintext. Recovery runs $600–$900; chip-off on the same drive costs $1,200–$1,500 & takes 2 to 4 weeks longer.